概述
串轉換在實際的電路中使用比較多，尤其在通信線路方面的復用和分解方面，原理上就是一個串轉換和並轉換的過程。舉個簡單的例子，計算機串口傳送數據的過程，如果滿足傳送條件了，其實就是一個並串轉換的過程了。
程式
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--Engineer:skycanny
--ModuleName:p2s-Behavioral
--Toolversions:ISE7.1
--Description:Thismoduleisdesignedtoimplementparalleltoserialconversion
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libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityp2sis
port(
reset:instd_logic;
clk:instd_logic;
start:instd_logic;--lowactive,data_invalid
data_in:instd_logic_vector(7downto0);
data_valid:outstd_logic;--highactive,outputdatavalid
ready:outstd_logic;--lowactive,readytorecievedata
q:outstd_logic
);
endp2s;
architectureBehavioralofp2sis
signalreg:std_logic_vector(7downto0);
signalcnt:std_logic_vector(3downto0);
signalreg_en:std_logic;
signalshift_start:std_logic;
typestateis(idle,recieve,shift,finish);
signalcurrent_state,next_state:state;
begin
counter:process(reset,clk,shift_start)
begin
if(reset="0")then
cnt'0');
elsif(clk'eventandclk="1")then
if(shift_start="0")then
cnt'0');
endif;
endif;
endprocesscounter;
fsm:block
begin
sync:process(reset,clk)
begin
if(reset="0")then
current_state
ready
reg_en
reg_en
reg_en
next_state'0');
q<="0";
elsif(clk'eventandclk="1")then
if(reg_en="0")then
reg<=data_in;
elsif(shift_start="0")then
q<=reg(7);
foriin7downto1loop--shiftregister
reg(i)<=reg(i-1);
endloop;
reg(0)<="0";
else
q<="0";
endif;
endif;
endprocessdata_channel;
endBehavioral;
