G3―主機板上只有電池供電；
S0--實際上這就是我們平常的工作狀態，所有設備全開，功耗一般會超過80W；
S1--也稱為POS（Power on Suspend），這時除了通過cpu時鐘控制器將CPU關閉之外，其他的部件仍然正常工作，這時的功耗一般在30W以下；（其實有些CPU降溫軟體就是利用這種工作原理）
S3--這就是我們熟悉的STR（Suspend to RAM），這時的功耗不超過10W；
S4--也稱為STD（Suspend to Disk），這時系統主電源關閉，但是硬碟仍然帶電並可以被喚醒；
S5--這種狀態是最乾脆的，就是連電源在內的所有設備全部關閉，功耗為0。
我們最常用到的是S3狀態，即Suspend to RAM（掛起到記憶體）狀態，簡稱STR。顧名思義，STR就是把系統進入STR前的工作狀態資料都存放到記憶體中去。在STR狀態下，電源仍然繼續為記憶體等最必要的設備供電，以確保資料不丟失，而其他設備均處於關閉狀態，系統的耗電量極低。一旦我們按下Power按鈕（主機電源開關），系統就被喚醒，馬上從記憶體中讀取資料並恢復到STR之前的工作狀態。記憶體的讀寫速度極快，因此我們感到進入和離開STR狀態所花費的時間不過是幾秒鐘而已；而S4狀態，即STD（掛起到硬碟）與STR的原理是完全一樣的，只不過資料是保存在硬碟中。由於硬碟的讀寫速度比記憶體要慢得多，因此用起來也就沒有STR那�快了。STD的優點是只通過軟體就能實現，比如Windows 2000就能在不支援STR的硬體上實現STD。
二.G3 S5時序
1. G3：表示主機板還沒有插上ATX POWER 的狀態。主機板上只有電池供電
S5：表示主機板有插上ATX POWER，但沒有按下power button的狀態.此時主機板上有5VSB和電池供電
相關聯信號腳的描述
| name | description |
| VCCRTC | 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well (1 pin). This power is not expected to be shut off unless the RTC battery is removed or completely drained. NOTE: Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Clearing CMOS in an ICH6-based platform can be done by using a jumper on RTCRST# or GPI. |
| RTCRST# | RTC Reset: When asserted, this signal resets register bits in the RTC well.NOTES:1. Unless CMOS is being cleared (only to be done in the G3 power state), the RTCRST# input must always be high when all other RTC power planes are on.2. In the case where the RTC battery is dead or missing on the platform, the RTCRST# pin must rise before the RSMRST# pin. |
| V5REF_SUS | Reference for 5 V tolerance on resume well inputs (1 pin). This power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile configurations. |
| VCCSUS3_3 | 3.3 V supply for resume well I/O buffers (20 pins). This power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile configurations. |
| VCCSUS1_5 | 1.5 V supply for resume well logic (3 pin). This power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile configurations.This voltage may be generated internally (see Section 2.22.1 for strapping option). If generated internally, these pins should not be connected to an external supply. |
| LAN_RST# | LAN Reset: When asserted, the internal LAN controller will be put into reset. This signal must be asserted for at least 10 ms after the resume well power (VccSus3_3 and VccSus1_5 in desktop and VccLAN3_3 and VccLAN1_5 in mobile) is valid. When de-asserted, this signal is an indication that the resume (LAN for mobile) well power is stable. NOTE: LAN_RST# must de-assert at some point to complete ICH6 power up sequencing. |
| RSMRST# | Resume Well Reset: This signal is used for resetting the resume power plane logic. |
1)破解BIOS密碼的好招
2)CMOS放電
目前的主機板大多數使用紐扣電池為BIOS提供電力，也就是說，如果沒有電，它裡面的資訊就會丟失了。當它再次通上電時，BIOS就會回到未設定的原始狀態，當然BIOS密碼也就沒有了。
3) BIOS與CMOS
BIOS是軟體，CMOS是硬體，簡單說CMOS是BIOS的載體
BIOS，完整地說應該是ROM－BIOS，是唯讀記憶體基本輸入／輸出系統的縮寫，它實際上是被固化到微機主機板ROM晶片上的一組程式，主要保存著有關微機系統最重要的基本輸入輸出程式，系統資訊設定、開機上電自檢程式和系統啟動程式等；為電腦提供最低級的、最直接的硬體控制。準確地說， BIOS是硬體與軟體程式之間的一個“轉換器”或者說是介面(雖然它本身也只是一個程式)，負責解決硬體的即時需求，並按軟體對硬體的操作要求具體執行。 BIOS ROM 晶片不但可以在主機板上看到，而且BIOS管理功能如何在很大程度上決定了主機板性能是否優越。
CMOS-------互補金屬氧化物半導體
CMOS的用處很多，比如有的數位相機的感光器就是用CMOS的。CMOS是互補金屬氧化物半導體的縮寫。其本意是指製造大型積體電路晶片用的 一種技術或用這種技術製造出來的晶片。在這裡通常是指微機主機板上的一塊可讀寫的RAM晶片。它存儲了微機系統的實時鐘資訊和硬體設定資訊等，總計128個 位元組。系統在加電引導機器時，要讀取CMOS資訊，用來初始化機器各個部件的狀態。它靠系統電源和後備電池來供電，系統掉電後其資訊不會丟失。
BIOS和CMOS的作用和區別
而BIOS是基本輸入輸出系統的縮寫，指集成在主機板上的一個ROM晶片，其中保存了微機系統最重要的基本輸入輸出程式、系統開機自檢程式等。它負責開機時，對系統各項硬體進行初始化設定和測試，以保證系統能夠正常工作。由於CMOS與BIOS都跟微機系統設定密切相關，所以才有CMOS設定和 BIOS設定的說法。CMOS RAM是系統參數存放的地方，而BIOS中系統設定程式是完成參數設定的手段。因此，準確的說法應是通過BIOS設定程式對CMOS參數進行設定。而我們 平常所說的CMOS設定和BIOS設定是其簡化說法，也就在一定程度上造成了兩個概念的混淆。
3.VCCRTC的作用
電路如下：
VCCRTC供電用來保存CMOS設定中的資料不丟.
三. S5 S0時序
按下Power Button ,PWRBT- 訊號由High ->Low 觸發I/O chip,I/O chip 送出LED-BLK 為High 0.7v,使PS-ON 被拉Low 系統開機，其過程如下
一.G3 state S0 state
G3:主機板上沒有其他任何電源供電，只有電池供電
S0:開機狀態，所有設奮處於全開狀態
時序如下圖：
SUSCLK O:This clock is an output of the RTC generator circuit to use by other chips for refresh clock.
PWROK I: When asserted, PWROK is an indication to the ICH8 that all power rails have been stable for 99 ms and that PCICLK has been
stable for 1 ms. PWROK can be driven asynchronously. When PWROK is negated, the ICH8 asserts PLTRST#.
NOTE: PWROK must deassert for a minimum of three RTC clock periods in order for the ICH8 to fully reset the power and properly generate the PLTRST# output
VRMPWRGD I: This signal should be connected to be the processor’s VRM Power Good signifying the VRM is stable. This signal is
internally ANDed with the PWROK input. This signal is in the resume well.
SUS_STAT#O: This signal is asserted by the ICH8 to indicate that the system will be entering a low power state soon. This can be
monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. It can also be used by other
peripherals as an indication that they should isolate their outputs that may be going to powered-off planes. This signal is called LPCPD# on the LPC interface.
PLTRST# O: The Intel® ICH8 asserts PLTRST# to reset devices on the platform (e.g., SIO, FWH, LAN, (G)MCH, TPM, etc.). The ICH8
asserts PLTRST# during power-up and when S/W initiates a hard reset sequence through the Reset Control register (I/O Register CF9h). The ICH8 drives PLTRST# inactive a minimum of 1 ms after both PWROK and VRMPWRGD are driven high. The ICH8 drives PLTRST# active a minimum of 1 ms when initiated through the Reset Control register (I/O Register CF9h).
NOTE: PLTRST# is in the VccSus3_3 well.
CPUSLP# O: This signal puts the processor into a state that saves substantial power compared to Stop-Grant state. However, during
that time, no snoops occur. The Intel® ICH8 can optionally assert the CPUSLP# signal when going to the S1 state.
STPCLK# O: STPCLK# is an active low output synchronous to PCICLK. It is asserted by the ICH8 in response to one of many
hardware or software events. When the processor samples STPCLK# asserted, it responds by stopping its internal clock.
二.S0 state S5 state
時序如下圖：
