《現代處理器設計》作者：（美）謝（Shen，J.P.）等著
出版社：清華大學出版社
出版時間：2007-8-1
字數：
版次：1
頁 數：642
印刷時間：2007/08/01
開本：
印次：
紙張：膠版紙
ISBN：9787302153573
包裝：平裝
所屬分類：圖書>>計算機/網路>>硬體外部設備維修
內容簡介
本書是關於處理器設計的最新、最權威教材，主要論述了：（1）處理器的設計方法和原理；（2）流水線技術；（3）主存與I/O系統；（4）超標量組織與技術；（5）POWerPC620和IntClP6等示例；（6）超標量處理器設計；（7）先進的指令流技術、存儲器數據流技術；（8）多執行緒技術等。本書適合作為計算機及相關專業的“處理器設計”課程的教材，也是有關專業人員很有價值的參考用書。
章節
TableofContentsAdditionalResources
Preface
1ProcessorDesign
1.1TheEvolutionofMicroprocessors
1.2InstructionSetProcessorDesign
1.2.1 DigitalSystemsDesign
1.2.2 Architecture,Implementation,andRealization
1.2.3 InstructionSetArchitecture
1.2.4 Dynamic-StaticInterface
1.3PrinciplesofProcessorPerformance
1.3.1 ProcessorPerformanceEquation
1.3.2 ProcessorPerformanceOptimizations
1.3.3 PerformanceEvaluationMethod
1.4Instruction-LevelParallelProcessing
1.4.1 FromScalartoSuperscalar
1.4.2 LimitsofInstruction-LevelParallelism
1.4.3 MachinesforInstruction-LevelParallelism
1.5Summary
2PipelinedProcessors
2.1PipeliningFundamentals
2.1.1 PipelinedDesign
2.1.2 ArithmeticPipelineExample
2.1.3 PipeliningIdealism
2.1.4 InstructionPipelining
2.2PipelinedProcessorDesign
2.2.1 BalancingpipelineStages
2.2.2 UnifyingInstructionTypes
2.2.3 MinimizingPipelineStalls
2.2.4 CommercialPipelinedProcessors
2.3DeeplyPipelinedProcessors
2.4Summary
3Memoryandl/OSystems
3.1Introduction
3.2ComputerSystemOverview
3.3KeyConcepts:LatencyandBandwidth
3.4MemoryHierarchy
3.4.1 ComponentsofaModernMemoryHierarchy
3.4.2 TemporalandSpatialLocality
3.4.3 CachingandCacheMemories
3.4.4 MainMemory
3.5VirtualMemorySystems
3.5.1 DemandPaging
3.5.2 MemoryProtection
3.5.3 PageTableArchitectures
3.6MemoryHierarchyImplementation
3.7Input/OutputSystems
3.7.1 TypesofI/ODevices
3.7.2 ComputerSystemBusses
3.7.3 CommunicationwithI/ODevices
3.7.4 InteractionofI/ODevicesandMemoryHierarchy
3.8Summary
SuperscalarOrganization
4.1LimitationsofScalarPipelines
4.1.1 UpperBoundonScalarPipelineThroughput
4.1.2 InefficientUnificationintoaSinglePipeline
4.1.3 PerformanceLostDuetoaRigidPipeline
4.2FromScalartoSuperscalarPipelines
4.2.1 ParallelPipelines
4.2.2 DiversifiedPipelines
4.2.3 DynamicPipelines
4.3SuperscalarPipelineOverview
4.3.1 InstructionFetching
4.3.2 InstructionDecoding
4.3.3 InstructionDispatching
4.3.4 InstructionExecution
4.3.5 InstructionCompletionandRetiring
4.4Summary
5SuperscalarTechniques
5.1InstructionFlowTechniques
5.1.1 ProgramControlFlowandControlDependences
5.1.2 PerformanceDegradationDuetoBranches
5.1.3 BranchPredictionTechniques
5.1.4 BranchMispredictionRecovery
5.1.5 AdvancedBranchPredictionTechniques
5.1.6 OtherInstructionFlowTechniques
5.2RegisterDataFlowTechniques
5.2.1 RegisterReuseandFalseDataDependences
5.2.2 RegisterRenamingTechniques
5.2.3 TrueDataDependencesandtheDataFlowLimit
……
6 ThePowerPc620
7 Intel'sP6Microarchitecture
8 SurveyofSuperscalarProcessors
9 AdvancedInstructionFlowTechniques
10 AdvancedRegisterDataFlowTechniques
11ExecutingMultipleThreads
Index
